Silvaco Pioneers Integrated Solution to Nanometer Single Event Effect Failures

Santa Clara, June 7, 2004

Silvaco International today announced the release of ATLAS 2/3D Single Event Effects (SEE) Module and the SmartSpice-SEE Module. These have been integrated with the HIPEX Full-Chip Parasitic Extraction tools and HyperFault Mixed-Level Fault Simulator to provide a complete design flow to identify, analyze, and mitigate SEEs in analog, digital, and mixed-signal IC designs.

“The Silvaco integrated SEE solution provides analysis tools to identify and the methodologies to mitigate SEE failures,” said Ken Brock, vice president of marketing at Silvaco. “It provides semiconductor engineers with tools for complete SEE identification, characterization and verification.”

Basic SEE mitigation techniques include adding capacitance to a node, increasing drive strength, raising the voltage, and using redundant logic with voting. Each of these techniques can seriously impact performance—especially if used indiscriminately.

SEE analysis and mitigation techniques are appropriate at different levels of design. At the device level, a TCAD device simulator analyzes the physics behavior of a device being hit by an SEE. At the circuit level, a SPICE simulator predicts circuit behavior after an SEE. At the cell level, characterization tools develop the cell views that digital EDA tools use to synthesize, place, and route logic cells into blocks. At the block or chip level, a full-chip parasitic extractor determines which signals are susceptible to SEEs based on their node capacitance and resistance. Finally, a fault simulator determines if an SEE disrupts the logic behavior of the block or chip, based on the gate level netlist, stimulus/response test vectors, and capacitance thresholds.

“The SEE problems are similar to nanometer noise coupling issues except the aggressor is a random SEE,” stated Dr. Chris Nicklaw, vice president of research and development. “The integration of TCAD, circuit simulation, and mixed-level fault simulation tools are required to accurately identify, model, and mitigate SEE issues in nanometer processes.”

ATLAS 2/3D SEE Module

ATLAS Device Simulation enables device technology engineers to simulate the electrical, optical, and thermal behavior of semiconductor devices. The SEE Module enables engineers to vary the energy of the particle, where it hits the device, and the angle of penetration. The device’s response to SEEs is transferred to SPICE through a compact model or Verilog-A.

SmartSpice Circuit Simulator SEE Module

SmartSpice Analog Circuit Simulator delivers the highest performance and accuracy required to design complex analog circuits, analyze critical nets, characterize cell libraries, and verify analog mixed-signal designs. The SmartSpice-SEE module enables semiconductor engineers to build a library of SEE stimulus/response models in compact models or in Verilog-A.

HIPEX Full-Chip Parasitic Extraction

HIPEX Full-Chip Parasitic Extraction products perform 3D-accurate and 2D-fast extraction of parasitic capacitors and resistors from hierarchical layouts into hierarchical transistor-level netlists, with node thresholds, using nanometer process technology.

HyperFault Mixed-Level Verilog Simulator

HyperFault Mixed-Level Fault Simulator is a Verilog IEEE-1364-2001 compliant fault simulator that analyses test vectors’ ability to detect stuck-at and SEE faults using a fault dictionary. It supports mixed levels of gate, behavioral, and switch with SDF timing.

Pricing and Availability

Silvaco tools are available now on Linux and Solaris as well as Windows. Perpetual, time-based, and site licenses are available for workgroup configurations of these products. List price for a complete SEE solution starts at $500,000 for a term-based license. For further information on these products, please contact sales@silvaco.com.

For other information please contact:

Silvaco
408-654-4392