Silvaco at DAC: A/MS Simulation, Full-Chip Parasitic Extraction, RF Simulation, Library Characterization and Single Event Effect Reliability

Santa Clara, May 20, 2004

Silvaco International today announced that its activities at the 41st Design Automation Conference will include product demonstrations on analog/mixed-signal Verilog/SPICE simulation, PDK-enabled schematic-driven layout, full-chip parasitic extraction, library characterization and Single Event Effects (SEE) mitigation using TCAD, circuit simulation and fault simulation. Click here to make an appointment to see these demos.

Silvaco will participate on the Accellera-sponsored “OpenKit Initiative Breakfast Panel” on Monday, June 7th at 7:30AM with Ken Brock, Silvaco’s Vice President of marketing and Chairman of the GSA MS/RF Foundry Committee PDK working group.

Live demonstrations of Silvaco’s software products will include:

  • Harmony-AMS Analog/Mixed-Signal Simulation Platform delivers unsurpassed accuracy and productivity. Harmony-AMS is based on the Silos Verilog and SmartSpice Circuit simulators integrated into a single-kernel simulator that fully supports Verilog-AMS, Verilog, Verilog-A, and SPICE.
     
  • SmartSpice-RF Harmonic Balance-Based Simulator provides a complete set of steady-state analyses to design GHz range RF wireless application ICs. QUEST High Frequency Parasitic Extractor accurately characterizes RF inductors, capacitors, resistors and transmission lines.
     
  • HIPEX Full-Chip Parasitic Extraction products perform 3D-accurate and 2D-fast extraction of parasitic capacitors and resistors from hierarchical layouts into transistor-level netlists.
     
  • Schematic Driven Layout Design Flows with Gateway Schematic Editor driving the SmartSpice Circuit Simulator, Expert Layout Editor, Guardian DRC/LVS/LPE, and HIPEX parasitic extraction tools supported by Silvaco’s process design kits.
     
  • Library Characterization with SmartCell and SmartCore Characterization Tools generate the accurate timing and power models required by leading synthesis, HDL simulation, routing, and analysis tools.
     
  • Single Event Effects Mitigation Solution with ATLAS 2/3D-SEE Module and the SmartSpice-SEE Module integrated with the HIPEX Full-Chip Parasitic Extraction tools and HyperFault Mixed-Level Fault Simulator to provide a complete design flow to identify, analyze, and mitigate SEEs in mixed-signal IC designs.

 

For more information please contact:

Silvaco
408-654-4392