Silvaco Offers Free Open-Source Verilog-A Device Models

Santa Clara, March 2, 2004

Silvaco International today announced that seven key Verilog-A Active Device Models are available on its website for free download under open source distribution.

Complete source code of BSIM3, BSIM4, EKV, and LEVEL3 for CMOS, Gummel-Poon, Mextram, and VBIC for bipolar, RPI-TFT for TFT, and Diode are compliant to Verilog-AMS 2.1 from Accellera, derived from IEEE 1364-2001 Verilog HDL specification.

“The Compact Modeling Council (CMC) is a group of semiconductor vendors and EDA vendors that promote standardization of compact model formulations”, said Joe Watts, chairman of the CMC. “The CMC fully supports efforts like these that facilitate communication between EDA vendors and their customers. By using open source, information can be transferred quickly between companies and allow for much faster evaluation of improvements made to SPICE models..”

“Silvaco’s offering of these models in open source affirms the use of Verilog-A for compact model development,” said Vassilios Gerousis, chairman of the Technical Coordinating Committee for Accellera.. “Verilog-A models can be used by semiconductor manufacturers, foundries, fabless designers, universities, and research organizations to significantly improve the quality of today’s compact models for tomorrow’s semiconductor processes.”

“True interoperability happens when market leaders adopt worldwide standards and open interfaces,” said Ken Brock, vice president of marketing at Silvaco. “These models enable semiconductor vendors and their customers to exchange both public and proprietary models that are simulator independent.”

Using Verilog-A for Compact Model Development and Distribution

All SPICE circuit simulators use compact models to accurately model the behavior of each primitive device such as transistors, diodes, capacitors, inductors and resistors in a given semiconductor process. SPICE models are typically written in the “C” language and compiled directly into the SPICE program. The problem is that any changes to the model source code require that the SPICE simulator models must be recompiled, re-linked, verified, and distributed resulting in customers not receiving these improvements for many months.

Using Verilog-A as a compact model development platform, model developers without access to SPICE simulator source code can study, develop, improve, and verify compact models in an interactive debugging environment. When completed, the Verilog-A model can be compiled for performance and dynamically linked into a SPICE simulator as a new model. This enables semiconductor manufacturers and their customers to share both public and proprietary models and verify them with multiple SPICE simulators using the same models.

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