Stress Effect on ETSOI IV characteristics

vsex05.in : Stress Effect on ETSOI IV characteristics

Requires: Athena Victory Stress and Atlas
Minimum Versions: Athena 5.21.2.R, Victory Stress 2.4.8.R, Atlas 5.19.20.R

Extremely thin SOI (ETSOI) devices are attractive for low power applications. The integration scheme of the ETSOI technology allows formation of raised source/drain (RSD) extensions for both NFET and PFET by using a single mask. Another feature of ETSOI CMOS is the combination of two strain enhancement techniques, (1) Si:C RSD for NFET and SiGe RSD for PFET, and (2) stress liner effect coupled with faceted RSD.

Details and features of the ETSOI CMOS can be found in [1], [2]. Please refer to vsex04.in for a comprehensive description of the stress simulation.

The 2D structure is created in Athena and subsequently used in Victory Stress. In this example we compare, IV characteristics obtained using Atlas, with stress-liner made of nitride with two geometries of RSD (vertical and faceted).

Aside from the standard silicon models (cvt, srh, etc), we used the strain dependent mobility enhancement models nhance and phance defined in the mobility statement for this simulation. The mobility enhancement models apply the second order mobility enhancement tensor (calculated by Victory Stress) directly to the low field mobility. This results in directionally dependent (anisotropic) electron and hole mobilities. For the model to take effect the enhancement factors must be included in the structure file simulated by Victory Stress. This is done by setting nhance and phance defined in the mobility statement of Victory Stress.

Electrical simulations show that the effect of stress/strain results in drive current increase and as shown in [2] higher increase with faceted RSD.

To load and run this example, select the Load example button in DeckBuild Examples window. This will copy the input file and any support files to your current working directory. Select the Run button to execute the example.

[1] K. Cheng, et al, Symp. VLSI Tech, 2009, p.212

[2] K. Cheng, et al, IEDM 2009, p. 49