Effects of Stress/Strain on a 50 nm Silicon FinFET

vsex02.in : Effects of Stress/Strain on a 50 nm Silicon FinFET

Requires: Victory Process, Victory Stress and Victory Device
Minimum Versions: Victory Process 7.6.8.R, Victory Stress 2.4.8.R, Victory Device 1.5.4.R

In modern semiconductor devices, the effects of physical lattice strain are playing an increasingly important role. One reason for this is that as device dimensions have shrunk, strains due to lattice mismatch or differences in thermal expansion have become more prevalent. Another is that strain has become an important tool in modifying and enhancing the electrical properties of the semiconductor materials. Large strain induced gains in both electron and hole mobilities have been reported.

This example demonstrates how SILVACO tools can be used to simulate the creation of a 3D FinFET using Victory Process, calculate the internal strains using Victory Stress, and analyze its electrical characteristics using Victory Device.

Victory Process was used to generate the FinFET structure based on specifications provided in a mask layout file using the Layout statement. Victory Process was used to build up a FinFET structure with a 50x50 nm fin, 1um in length. The fin was deposited on a SiO2 substrate layer and a 2 nm gate isolation layer separated it from the 50 nm polysilicon gate crossing it at right angles. A 100 nm Si3N4 capping layer was deposited on top of the structure.

The structure created by Victory Process was imported into Victory Stress, which was used to perform a stress analysis over the whole FinFET device structure. The Si3N4 capping layer was set to have uniform hydrostatic tensile stress of 1 GPa using the statement material nitride intrin.sig=1e10 The evaluation of mobility enhancement factors along the fin is based on a full 3D piezoresistive model.

The structure, along with the stress/strain and mobility enhancement data, was then loaded into Victory Device for electrical simulation and analysis. Source and drain electrodes were defined at either end of the Silicon fin, the Polysilicon region was defined to be the gate, and we put a substrate contact at the bottom of the device. We also set the workfunction of the gate to 4.17 eV.

Aside from the standard silicon models (cvt, consrh, etc), we used the strain dependent mobility enhancement models nhance and phance defined in the mobility statement for this simulation. The mobility enhancement models apply the second order mobility enhancement tensor (calculated by Victory Stress) directly to the low field mobility. This results in directionally dependent (anisotropic) electron and hole mobilities.

Electrical simulations show that the effect of stress/strain results in drive current increase as expected.

To load and run this example, select the Load example button in DeckBuild Examples window. This will copy the input file and any support files to your current working directory. Select the Run button to execute the example.