TCAD to SPICE - 6T SRAM SEU Simulation

radex14.in : TCAD to SPICE - 6T SRAM SEU Simulation

Requires: Deckbuild / VictoryProcess2D / DevEdit 3D / VictoryDevice3D / SmartSpice
Minimum Versions: Deckbuild 3.44.19.R / VictoryProcess 7.6.6.R / Devedit 2.8.23.R / VictoryDevice 1.8.2.R / SmartSpice 4.19.28.A

This examples demonstrates how the response of a single transistor to a Single Event Strike, can first be simulated and calibrated using physics based TCAD simulation, and then how this exact response can be extracted into a data file and incorporated directly into user specified circuit nodes of a Spice circuit simulation, for fast Spice analysis of a circuit to Single Event Upsets.

The example demonstrates how this entire TCAD to SPICE flow can be simulated with just a single input file, executed in it's entirety in the deckbuild run time environment, without any intermediate input required from the user.

The example simulates the response of a single 65nm n-channel MOSFET to a Single Event Strike using physically based TCAD simulation. The terminal response from this TCAD simulation, is then captured in a data file. This MOSFET response to the Single Event Strike can then be passed to a 100% SmartSPICE simulation to evaluate the whole circuit response to a strike. Since the simulation is now 100% Spice, the total circuit simulation time of a Single Event Strike is just a few seconds for a logic cell sized circuit. This allows many simulations of multiple Single Events, occurring in any transistor in any circuit, occurring at any time, once the response to a particular strike has been calibrated using physics based TCAD.

The 65nm SRAM is simulated in it's low power state, where the supply voltage is reduced to 0.85 volts, as this represents the SRAM's most sensitive configuration to a Single Event Effect.

The data flow in this particular example occurs in the following sequence:

  • Start with a trusted Spice model from the foundry PDK that you are currently using.
  • Using this PDK Spice model, simulate basic DC characteristics of the device type that is to be tested using a Single Event Strike, such as unsaturated and saturated threshold voltage, IdVd curve sets etc.
  • Create a TCAD model of the device to be tested, and use the Spice generated DC characteristics above, to ensure that the TCAD simulations are a reasonable match to the Spice generated curves.
  • In TCAD, then simulate one or more strike events and capture the device response by extracting a data file of time/current pairs.
  • The time/current pairs data file captured above, is then loaded into a pure Spice simulation as a time dependent current source at the circuit node under test, so the response of the whole circuit to a Single Event Strike can now be simulated directly in Spice. Multiple strikes at different times on different devices in the circuit can also be simulated using the same data file.

With the data flow above in mind, the input file below goes through the following simulation steps:

First, a two dimensional, 65nm nMOS device is simulated in VictoryProcess, which enables a faster simulation than creating a full 3D structure. The 2D structure is then extended into the third dimension using Devedit. The 3D structure is now loaded into VictoryDevice, where several DC simulations, characterise the basic device electrical behaviour, which can then be compared with the Spice model, to validate that similar behaviour has been obtained.

The energy of the Single Event Strike is characterized by a parameter called the "Linear Energy Transfer", or LET. The higher the LET, the greater the energy of the incoming particle or photon. In this example, the LET value of the incoming strike is set up as a variable, by the line "set LET=1", which creates a variable called "$LET" and assigns it a unity value. In order to convert the units of LET into units of pico Coulombs/cm3 of track charge density, the LET value needs to be multiplied by 0.01035 for silicon material. A second variable called "$density" is assigned this converted pico coulomb value. Lastly, the units of the strike are specified to be these same pico coulomb units, by the parameter "pcunits" in the "singleeventupset" statement that describes the time and track positional properties of the strike.

Once the Single Event Strike has been simulated, the time versus current data is extracted using an extract statement, into a file called radex14.dat. An important part of this extract statement is the new "no.header" option, which strips off the normal header associated with a standard Silvaco data file format, which is a requirement for the data file to be read directly by SmartSpice.

Simulation of a 6 transistor SRAM cell, with a Single Event Strike on one of the nMOS transistors, can now be simulated directly in SmartSpice using the newly creted data file. The strike can also be associated with a time delay before the strike occurs. This delay is implemented in the "VSEU" line of the SmartSpice section of the input file, and is specified using the "TD" parameter. In this simulation, the delay before the Single Event Strike is set to be 0.5 micro-seconds by setting the parameter "TD=0.5u" on the "VSEU" statement.

The huge advantage of importing the TCAD generated data file of the Single Event Strike, directly into Spice, is that each Spice simulation, now only takes a couple of seconds, so many strikes at different times and for different transistors, allows fast characterization of a circuit sensitivity to SEU upset events.

To load and run this example, select the Load example button in DeckBuild. This will copy the input file and any support files to your current working directory. Select the run button to execute the example.