Analyzer - Expandable vectors

033_analyzer_vectors : Analyzer - Expandable vectors

Minimum Required Versions: SILOS 4.12.1.C

Example 033_analyzer_vectors, the circuit is a newspaper vending machine implemented as a Verilog gate level design. The Gateway schematics for the testbench and circuit as well as the netlist and the library files vend.gv and abc_100.v.

This example shows the SILOS graphical user interface feature to expand a vector in the Analyzer window.

Analyzer - Expandable vectors

  • Open the project gate.spjx and run the simulation.
  • Open the Analyzer window from the toolbar.
  • Select info[96:1] of the stimulus module in the module tree in the Explorer window and drag and drop it to the Analyzer window to show the waveform.
  • Click on the plus (+) box to the left of the vector name "info[96:1]" to expand the individual bits for the vector.
  • Click on the minus (-) box to the left of the vector name again to hide the vector signal bits.