Analyzer - Signal state display

028_analyzer_state : Analyzer - Signal state display

Minimum Required Versions: SILOS 4.12.1.C

This example demonstrates the Analyzer Signal state display and State Change Hazard Feature.

Example 028_analyzer_state, the circuit is a newspaper vending machine implemented as a Verilog gate level design. The Gateway schematics for the testbench and circuit as well as the netlist and the library files vend.gv and abc_100.v.

This example shows the feature of the SILOS graphical user interface for Analyzer Signal state display and the State Change Hazard display

Analyzer - Signal state display

  • Open the project gate.spjx and run simulation.
  • Open the Analyzer window from toolbar.
  • Left click in the waveform window so that the blue marker is displayed.
  • Observe the signal states (values) at the marker time are displayed in the signal listbox.
  • Left click at a different time in the waveform window.
  • Observe the signal states (values) for the new marker time are displayed in the signal listbox.

Analyzer - State Change Hazard display

  • Open the project gate.spjx and run simulation.
  • Open the Analyzer window from toolbar.
  • Check the Display State Change Hazard feature checkbox.
  • When enabled, State Change Hazards are indicated by flashing red dots.
  • The tooltip shows the number of events occurred during the Hazard.