Analyzer - Drag & Drop

026_drag_and_drop : Analyzer - Drag & Drop

Minimum Required Versions: SILOS 4.12.1.C

This example demonstrates the Analyzer Drag & Drop features: Drag & Drop signal reordering, Drag & Drop from source edit window, Drag & Drop from module hierarchy browser.

Example 026_drag_and_drop circuit is a one bit adder implemented as a Verilog gate level design. The schematic consisting of gate level primitives and the Verilog netlist generated by Gateway are shown. The testbench source file contains Verilog behavioral code to generate the input test pattern.

The SILOS graphical user interface provides the features including Drag & Drop signal reordering, Drag & Drop from source edit windows, and Drag & Drop from module hierarchy browser in Analyzer.

Analyzer - Drag & Drop signal reordering

  • Open the project 1bit_adder.spjx and run the simulation.
  • Open the Analyzer window from the toolbar.
  • This project file already set some signals to display the Analyzer window.
  • Select one of the signals (e.g. "b" signal) and move it to the desired location for reordering the signal order while keeping the shift key pressed.
  • Alternatively, select one of the signals, and click the right mouse button to show the context menu.
  • Then select Move Item Up or Move Item Down.

Analyzer - Drag & Drop from source edit

  • Open the source file one_bit_adder.v and select one of the signals for which you want to see the waveforms.
  • Drag and drop it to the Analyzer signal list box.
  • In this example, select line 23 xor21 I1 Y connected signal "s1".

Analyzer - Drag & Drop from module hierarchy browser

  • Click the Explorer icon on the toolbar to open the Explorer window.
  • Select the module Stimulus.X1.I1 of the "Y" signal.
  • Drag & Drop the "Y" signal to display the waveforms. Since "s1" displayed above is equal to this "Y" signal, these waveforms are exactly the same.