Source Breakpoints

022_source_breakpoints : Source Breakpoints

Minimum Required Versions: SILOS 4.12.1.C

Example 022_source_breakpoints circuit is a one bit adder implemented as a Verilog gate level design. The schematic consisting of gate level primitives and the Verilog netlist generated by Gateway are shown. The testbench source file contains Verilog behavioral code to generate the input test pattern. The SILOS graphical user interface provides the source breakpoints feature.

Source Breakpoints

  • Open the project 1bit_adder.spjx.
  • Prior to running the step simulation, verify the "Enable Debugging" toolbar button is depressed to enable the debugging mode.
  • Click the toolbar button "Load/Reload Input Files" and open the stimulus file 1bit_testbench.v.
  • Click the left mouse button at the source line that you wish to set a breakpoint on.
  • In this case, click on the left side of line 19.
  • Click "Go" to start the simulation. This simulation will stop at line 19.
  • Observe the stimulus file 1bit_testbench.v source window, you will see the breakpoint and the yellow arrow (current source line indicator) are shown at line 19.