Single step mode

021_single_step : Single step mode

Minimum Required Versions: SILOS 4.12.1.C

Example 021_single_step circuit is a one bit adder implemented as a Verilog gate level design. The schematic consisting of gate level primitives and the Verilog netlist generated by Gateway are shown. The testbench source file contains Verilog behavioral code to generate the input test pattern. The SILOS graphical user interface provides the single step mode feature.

Single step mode

  • Open the project 1bit_adder.spjx.
  • Prior to running the step simulation, verify the "Enable Debugging" toolbar button is depressed to enable the debugging mode.
  • Click the toolbar button "Load/Reload Input Files", then the Step button will be enabled.
  • Next, click the Step button or press the F7 function key. One click will run one step of the source code execution.
  • Single step mode is helpful for the step debugging purpose.
  • If some signals will be shown into Analyzer, you can check the waveform step by step by clicking the Step toolbar button (or F7).
  • The yellow arrow is the positioned at the next source code line to be executed.