Reload and Go option

020_reload_and_go : Reload and Go option

Minimum Required Versions: SILOS 4.12.1.C

Example 020_reload_and_go circuit is a one bit adder implemented as a Verilog gate level design. The schematic consisting of gate level primitives and the Verilog netlist generated by Gateway are shown. The testbench source file contains Verilog behavioral code to generate the input test pattern. The SILOS graphical user interface provides the Reload and Go option.

Reload and Go option

  • Open the project 1bit_adder.spjx, and first run the simulation for this project.
  • Open the source code file one_bit_adder.v. As this picture shows, modify the file to add the inverter at the final stage.
  • When the file is saved, the "Reload and Go" toolbar button will be available for use.
  • Click the "Reload and Go" toolbar button.
  • This button reloads the source files and automatically runs the simulation.
  • Alternatively, you can use the menu item Debug->Reload and Go or the ALT+F5 function keys.