Source file reload

019_source_reload : Source file reload

Minimum Required Versions: SILOS 4.12.1.C

Example 019_source_reload circuit is a one bit adder implemented as a Verilog gate level design. The schematic consisting of gate level primitives and the Verilog netlist generated by Gateway are shown. The testbench source file contains Verilog behavioral code to generate the input test pattern. The SILOS graphical user interface provides the feature to reload source files.

Source File Reload