Project File Contains Simulation Control Settings

013_project_file : Project File Contains Simulation Control Settings

Minimum Required Versions: SILOS 4.12.1.C

Example 013_project_file, the circuit is a newspaper vending machine implemented as a Verilog gate level design. The Gateway schematics for the testbench and circuit as well as the netlist and library file are shown.

  • Start SILOS and open the project file "vend_tb.spjx" and click "Go" to run the simulation.
  • Open the Edit->Project Properties dialog.
  • Open the Analyzer waveform viewer and observe the color (green) of the reset signal and the radix (binary) used to display the values of the vector coin[1:0].
  • View the project file and note the XML nodes (e.g. <sourcefiles>, <libraryfiles>, <groups>) and elements in these nodes correspond to the settings in the Project Properties dialog.