Incremental Fault Simulation

004_incremental : Incremental Fault Simulation

Minimum Required Versions: Hyperfault 4.12.1.C

Example 004_incremental is a drink vending machine implemented as a Verilog gate level design. Included in this example are the Gateway schematic for the circuit as well as the testbench and library files are "dm_lib.v" and "primitives.v".

We will use the Hyperfault GUI to run a incremental fault simulations by simulating the same circuit with different test patterns. Hyperfault can use the results from prior fault simulations to reduce the fault set for subsequent fault simulations. This can speed up the later fault simulations as fewer faults need to be simulated.

Run Initial Fault Simulation with Partial Pattern

  • Start Hyperfault (command: hyperflt -gui), open the project file "flt_test.spjx"
  • Click "Start Fault Sim" to run the fault simulation.
  • Observe the fault simulation output in the Output window . Note that the example was run with the "Partial" test pattern.

Run Fault Simulation with Full Pattern

  • Start Hyperfault (command: hyperflt -gui), open the project file "flt_test.spjx"
  • Define the text macro "FULL_PATTERN" by defining the text macro in the Edit->Project Properties->PlusDefines dialog.
  • Open the Edit->Project Properties->Fault Simulation->Options dialog.
  • Select "Accumulate Detections" and "Undetected" options in the Iteration Controls section of the dialog.
  • Close the dialog by clicking "Ok".
  • Click "Start Fault Sim" to run the fault simulation.
  • Observe in the fault simulation output related to Iteration control. Note that 25 faults already simulated will not be run for this fault simulation.
  • Observe the accumulative fault simulation output in the Output window. Once again, reducing the fault set by faults found in prior fault simulation runs should reduce the run times of subsequent runs.