Logic Simulation and Activity Report

001_activity : Logic Simulation and Activity Report

Minimum Required Versions: Hyperfault 4.12.1.C

Example 001_activity is a drink vending machine implemented as a Verilog gate level design. Included in this example are the Gateway schematic for the circuit as well as the testbench and library files are "dm_lib.v" and "primitives.v".

It is suggested that prior to running a fault simulation on a circuit, the user should run a logic simulation and verify that the test pattern toggles as many of the nodes in the DUT as possible. Using the Activity reports to improve test pattern coverage is more efficient than running faults simulations.

Run a logic simulation using a partial stimulus pattern

  • Start Hyperfault (command: hyperflt -gui), open the project file "flt_test.spjx"
  • Open the testbench.v file and observe that the test pattern is truncated if the text macro "FULL_PATTERN" is not defined.
  • Click "Go" to run a logic simulation.
  • Observe the output from the simulation is written to the Hyperfault output window.
  • Open the toggle report by selecting the menu item Reports->Activity->Toggle
  • Observe the number of inactive nodes in the Summary section of the Toggle report.

Run a logic simulation using the full stimulus pattern

  • Start Hyperfault (command: hyperflt -gui), open the project file "flt_test.spjx"
  • Define the text macro "FULL_PATTERN" by editing the testbench file or by defining the text macro in the Edit->Project Properties->PlusDefines dialog.
  • Click "Go" to run the logic simulation.
  • Observe the output from the simulation is written to the Hyperfault output window.
  • Open the toggle report by selecting the menu item Reports->Activity->Toggle
  • Observe the number of inactive nodes in the Summary section of the Toggle report . The updated test pattern has fewer nodes that do not toggle and should give better coverage for a fault simulation.