Verilog top level PLL example

007_pll_verilog : Verilog top level PLL example

Minimum Required Version: Harmony 4.12.2.C

This example includes a top level Verilog netlist and a Phase Detector module, a Divider module which is implemented with Verilog-HDL, a SPICE top file which controled SPICE commands, SPICE netlists for Charge Pump and Low Pass Filter module, a Verilog-A VCO module and a Digital to Analog (or opposite) converter connect module. Also included is the final stage of an Inverter which was created from the Gateway schematic entry tool.

Simulate Verilog top level PLL example using Harmony.

  • Start Harmony and open the project pll_v.spjx and confirm the Harmony window title is displaying <project_path>/pll_v.spjx.
  • Check "Edit" -> "Project Properties" -> "Source Files" context dialog.
  • Run the simulation using the Go toolbar button.
  • Open the Explorer window by selecting "View" -> "Explorer" to view the circuit modules.
  • Open the Analyzer waveform viewer by selecting "View" -> "Analyzer" to view the simulation results.
  • In the Explorer window, select dut:PLL_TOP_V and select all signals, then drag and drop to the Analyzer signal window to view the simulation results.
  • For the final stage of Inverter, you can also review the simulation results, with drag and drop Inverter's "IN" and "OUT" pins.