Tristate Buffer example

006_tristate : Tristate Buffer example

Minimum Required Version: Harmony 4.12.2.C

This example includes a SPICE top-level testbench and , Verilog modules to create a random data streams to drive the input pins of the SPICE tristate subcircuits. The files used for this project are the SPICE netlist top.net, the SPICE model file models.spi, the Verilog netlist CORE.v and the connect module BiElecCon.v

Simulate the tristate circuit using Harmony.

  • Start Harmony and open the tristate.spjx project. The Harmony window title will now display <project_path>/trisate.spjx.
  • Run the simulation using Go toolbar button.
  • Open the Explorer window View->Explorer to view the circuit hierarchy.
  • Open the Analyzer waveform viewer to view the simulation results.