D-type Flip-Flop Verilog-A example

003_dff_a : D-type Flip-Flop Verilog-A example

Minimum Required Version: Harmony 4.12.2.C

In this D-type Flip-Flop behavioral model example we will look at the Verilog-A module definition and its simulation in Harmony. A Verilog-AMS testbench is used to define the analog signal sources and place the Verilog-a module definition of the D-type Flip Flop. The Harmony mixed-signal simulator will simulate the Verilog-a module in the analog simulator, (SmartSpice code) built-in to Harmony. The analog input and output signals are displayed in Harmony's design Explorer and waveform Analyzer.

Start Harmony and open the dff_a.spjx project File->Open Project for the Verilog-A DFF module example. The Harmony window title should now display the <project_path>/dff_a.spjx . To see the source files used by this project select Edit->Project Properties.

The project files are; main_a.in the SPICE analog control file, testbench_a.v the verilog top-level testbench with instantiation of the dff_a.vams module, and dff_a.vams the DFF verilog-a (ams) module itself. Open each of these files using the open file icon or File->Open.

The testbench Verilog module contains the usual `timescale definition and the `include "disciplines.vams" definition for the inclusion of disciplines and natures to be available for modeling. The analog ports d, clk, q for the instance DFF1 (dff_a) are defined as using the data flow voltage discipline rather than the usual electrical discipline. The voltage discipline does not model the current flow/feedback of the connecting load's nets or ports and is a simpler/faster modeling scheme than the full electrical (potential & flow) discipline. The signal sources for d, and clk inputs are instantiated using verilog-ams syntax,

module_name #(parameters) instance_name(ports);

On DFF1 instance we have specified the dir( -1) parameter making it negative edge triggered. The dff_a module is a purely Verilog-A analog module definition. The inputs and outputs use the analog voltage discipline while the DFF behavior is captured in the analog begin end block.

The main_a.in file is a SPICE control file giving the length of the simulation as 100ns with a guideline timestep of 10ps. Run the simulation and it should complete in a few seconds showing your output log.

To view the results turn on the Explorer View->Explorer and the Analyzer View->Analyzer . The signals should already be displayed because the dff_a.spjx project file contains the Analyzer signal list.

To add more signals to the Analyzer pane, select them from the Explorer pane on the left and right click to select Add Signals to Analyzer. Browse to the state signal and add it to your Analyzer. If you zoom in very close to the transitions around 25ns you will see that they are truly analog signals with rise and fall times. The red sine wave symbol before the signal name tells us that they are analog signals in Harmony.