Ripple Carry Counter Schematic Simulation

004_ripple_carry_counter : Ripple Carry Counter Schematic Simulation

Minimum Required Versions: Gateway 2.12.10.R, SILOS 4.10.90.R

Example 4 is a four bit ripple carry counter schematic. The top level of the design ( top_level.png ) is made from negative edge-triggered T flip flops. Descending one level down, the schematic ( tff.png ) is built with inverters and negative edge-triggered DFFs. The inverter and DFF cells both use attached file module definitions. The module definition for the DFF with synchronous reset is shown in dff_sr.v. The stimulus module, or test bench, is shown in the ripple_carry_counter.ctrv file ( ripple_carry_counter.ctrv). In this file, the top level design is instantiated and the output is monitored. Finally, the output waveforms are shown for the simulation ( waveforms.png ).