One Bit Adder Schematic Simulation

003_one_bit_adder : One Bit Adder Schematic Simulation

Minimum Required Versions: Gateway 2.12.10.R, SILOS 4.10.90.R

Example 3 is a one bit adder verilog design. The schematic ( schematic.png ) is shown consisting of gate level primitives and one_bit_adder.v is the resulting structural verilog netlist generated by Gateway (see one_bit_adder.v). The control file is the stimulus module that instantiates the adder design and simulates it ( one_bit_adder.ctrv). Running the design in SILOS produces the waveforms shown in Smartview ( waveforms.png ). The adder design can be folded up hierarchically to realize a larger design. By generating symbol views from schematic views, the one bit adder can be used to build a 2 bit adder ( 2bit_adder.png ), a 4 bit adder ( 4bit_adder.png ), and an 8 bit adder ( 8bit_adder.png ).