Inherited Nets with Explicit Pins Schematic

011_inherited_nets_explicit : Inherited Nets with Explicit Pins Schematic

Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R

This example illustrates use of inherited nets on logic symbols that have explicit pins for power, substrate, and ground (see schematic.png ). In this example, we define vdd as 5v and vdda as 3v. Using the net property: [PWR]=[vdda] on X2, we override the connected signal (VDD) with VDDA and pass in 3v instead of the 5v that supplies VDD.

Clicking on the lower_level_X2.png X2 inverter and pressing the D key descends to the lower level. The percent sign [%] in the netexpressions denotes that unless the net property has been defined at a higher level, use the normal name for the net.

In this example, the netexpression [PWR]:[%] means this: For X1, no net property for PWR exists, so X1 uses the normal connection for the net which is VDD. For X2, however, a net property exists defined as [PWR]=[VDDA], so VDDA is used and overrides the VDD connection on this subcircuit.

The netlist ( netInh_logic_explicit.net)shows how VDDA is used for X2. The wave forms (see waveforms.png ) display the inverter output at VDD (5V) and X2 override at 3V.