009_cell : Minimum Pulse Width Characterization

Minimum Required Versions: AccuCell 2.6.0.R, SmartSpice 4.6.2.R

This example explains the basics of AccuCell's minimum pulse width characterization and modeling options for a basic D Flip-Flop with rising edge clock using the embedded SmartSpice SPICE engine to perform characterization.

Minimum pulse width constraints are necessary to assure that the master/slave internal data transfer has adequate gating time to complete sucessfully. This places requirements on clock valid high and clock valid low condition timing. This is commonly measured by measuring the 50% point timing between rising and falling edges of the clock signal for various clock input slopes. Either a scalar value or a 1D vector as a function of slope are generated in the timing model.

AccuCell has the following .cfg file commands to control and specify these characterization and modeling parameters:

CALC_MPW, OUTPUT_SINGLE_MPW_VALUE, MPW_SLOPE_TABLE, and SETHOLD_MPWLEV.

CALC_MPW controls enabling minimum pulse width characterization.

OUTPUT_SINGLE_MPW_VALUE controls which type of Liberty .lib timing model format to use for minimum pulse width modeling between either a single scalar value or a 1D vector slope indexed table. Independent of this setting of this paramater characterization tests all defined slope conditions. In the case of a single scalar value AccuCell selects the largest value.

MPW_SLOPE_TABLE specifies the set of slopes to test for minimum pulse width characterization.

SETHOLD_MPWLEV specifies the relative operating voltage vs SUPPLY_V_HIGH to be used for minimum pulse width characterization. A value less than 1.0 permits 'runt' pulse characterization effects to be taken into account.

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