AccuCell Configuration Files

001_cell : AccuCell Configuration Files

Minimum Required Versions: AccuCell 2.6.0.R, SmartSpice 4.6.2.R

This example explains the basic AccuCell design flow and modeling options for creating NLDM, NLPM, CCS Timing and Verilog simulation with timing models for a simple inverter cell using the embedded SmartSpice SPICE engine to perform characterization.

The input files in this example are SmartSpice format netlists and models. Additional formats and external SPICE simulators are supported.

Two files control characterization and model generation:

Cell_EX1.cfg

the library level config file defines global parameters that apply to all cells unless overridden by

inv.cfg

which contains cell level parameters

Library level .cfg commands MOSFET_TYPE, LIB_CMD, SUPPLY_V_HIGH, TEMP are the main method of controlling the global PVT of the characterization process. When processing case-sensitive files

PRESERVE_CASE 1

MUST be the FIRST statement in the library level Cell_EX1.cfg file. A simple one line Cell_EX1.tcl file is used to define the cell.list and library level Cell_EX1.cfg file to use for the job. Any other valid .tcl scripting is permitted for additional automation control of the characterization and file management process for advanced users, but is NOT required for basic AccuCell operation.

Cell specific files are placed in a separate sub-directory of the same name as the cell name. The inv.cfg file in the inv sub-directory contains the cell level local details of the pins, conditions, file pointers and other data specific for that cell. IN_FILE_NAME, INPUTS, OUTPUTS, INOUTS, CLOCKS, POWERS, GROUNDS are the main .cfg parameters to define basic cell details.

For this inverter example, pin A is the input pin which is characterized for input capacitance when the library level Cell_EX1.cfg file includes the CALC_C_EFF 1 statement. Pin Y is the output pin which is characterized for delay and power for four slopes and four loads yielding 4x4 tables with indexes defined manually by the SLOPE_TABLE, CAP_TABLE Cell_EX1.cfg file statements. The cell netlist is defined in the inv_lvs.net.

Results for each cell appear in each cell's respective cell sub-directory. Results will also be grouped together for the entire characterization run into a library level file as well.

A Liberty inv_sps.lib Timing characterization model can be generated by specifying synthesis as a MODEL_TYPE in the library level Cell_EX1.cfgfile. In the case of Non-Linear-Delay-Model (NLDM) table models, the reported values are cell rise and fall delays and edge rise and fall transition times in a 2D slope and cap load indexed table.

The file inv.schlr is the Gateway schematic for the cell. A plot of the schematic is included in inv.png .

To run the example type run in a write-able directory with a copy of the example files.

All cells can be run as a group or individually by editing the cell.list file as desired. Cells in this file can be excluded by placing a "#" in front of the cell's name. Each cell must remain on a separate line.