Verilog/VHDL Simulator Developers

Hsinchu, Taiwan

Aggressively develop next-generation, Verilog/VHDL simulator. Work in a core team of elite software developers (coders) to develop and document state-of-the-art simulators.

Must have:

• Minimum MS in CS/EE with at least 5 years of relevant Verilog simulator development experience
• Must be highly proficient with C/C++, different operating systems and software development processes

Please quote ref. SW-VVHDL-TW when applying

By Email: jobs@silvaco.com